1. Field of the Invention
The present invention concerns a method of manufacturing a semiconductor memory device and, more in particular, it relates to a method of manufacturing a non-volatile semiconductor memory device having floating gate.
2. Description of Related Art
As a non-volatile semiconductor memory device capable of retaining stored date even after a power source is turned off, a non-volatile semiconductor memory device having a floating gate has been known. Such a non-volatile semiconductor memory device can write and erase stored data by accumulating and discharging electric charges to and from the floating gate.
Further, a split gate non-volatile semiconductor memory device has been proposed as a sort of a non-volatile semiconductor memory device having the floating gate (for example, refer to JP-A-2004-200181 and JP-A-2004-214411). FIG. 10 shows a split gate non-volatile semiconductor memory device described in JP-A-2004-200181.
As shown in FIG. 10, a source diffusion region 32 and a drain diffusion region 33 are formed to the surface layer of a silicone substrate 31. Further, a floating gate 35 is formed by way of a gate oxide film 34 above the silicon substrate 31. A control gate 36 is electrically insulated by a tunnel oxide film 37 from the floating gate 35. A portion of the floating gate 35 opposed to the control gate 36 has a shape pointed at a distal end (Tip portion 35a).
In the split gate non-volatile semiconductor memory device shown in FIG. 10, writing is carried out by injection of hot electrons generated by a high-voltage applied between the source diffusion region 32 and the drain diffusion region 33 to the floating gate 35 surmounting the energy barrier from the surface of the silicon substrate 31 to the oxide film. Further, erasing is carried out by drawing out the electrons injected in the floating gate 35 to the control gate 36. Particularly, a strong electric field is generated at the periphery of the Tip portion 35a due to the shape thereof and the electrons move mainly from the Tip portion 35a to the control gate 36. As described above, the Tip portion 35a improves the efficiency of the drawing out the electrons upon erasing.
Then, a method of manufacturing the split gate non-volatile semiconductor memory device shown in FIG. 10 is to be described with reference to FIG. 11. As shown in FIG. 11A, a first NSG spacer 39 and a second NSG spacer 40 are formed above a polysilicon film 38 for a floating gate. The first NSG spacer 39 is formed by etching back a tetraethoxy silane (TEOS)-Nondoped Silicate Glass (NSG) film and then shrunk fit by an annealing treatment to form a dense film. On the other hand, while the second NSG spacer 40 is formed in the same manner by etching back a TEOS-NSG film but subsequent annealing treatment is not applied. That is, the second NSG spacer 40 is formed as a film coarser than the first NSG spacer 39.
Further, an opening is formed to a portion of the polysilicon film 38, and the source diffusion layer 32 is formed corresponding to the opening. An insulative film is formed on the lateral surface and the upper portion of a polysilicon plug 41 above the source diffusion region 32. The insulative film on the lateral surface is formed by etching back the TEOS-NSG film, and the insulative film on the upper portion is formed by a thermal oxidation treatment.
Then, as shown in FIG. 11B, the polysilicon film 38 is selectively removed by using the first NSG spacer 39, the second NSG spacer 40, and the insulative film on the upper portion of the polysilicon plug 41 as a mask. The polysilicon film 38 left just below the first NSG spacer 39 and the second NSG spacer 40 by the etching constitutes the floating gate 35.
Then, as shown in FIG. 11C, the first NSG spacer 39 is removed by using a 5% hydrofluoric acid. Thus, the Tip portion 35a of the floating gate 35 is exposed.
Then, after forming the tunnel oxide film 37 so as to cover the exposed Tip portion 35a, a polysilicon film for the control gate is formed over the entire surface. Then, the control gate 36 is formed by etching back on the side wall of the second NSG spacer 40 and the floating gate 35 by way of the tunnel oxide film 37. Successively, an oxide film is formed over the entire surface and a sidewall insulative film is formed on the side wall of the control gate 36 by etching back. Then, after forming the drain diffusion region 33 by ion injection, the upper portion of the control gate 36 and the surface of the drain diffusion region 33 are silicided. As described above, the split gate non-volatile semiconductor memory device shown in FIG. 10 is formed.
Further, JP-A-2004-214411 discloses a method of manufacturing a split gate non-volatile semiconductor memory device different from that of JP-A-2004-200181. While the two spacers formed above the floating gate are formed only of the oxide film (NSG film) in JP-A-2004-200181, it is formed of a silicon oxide film and a silicon nitride film in JP-A-2004-214411. Further, in the manufacturing method of JP-A-2004-200181, while a sacrificial layer formed of a silicon nitride film is used on one side of the first NSG spacer before the step in FIG. 11A, a sacrificial layer formed of a polysilicon film is used in JP-A-2004-214411. Accordingly, the method of manufacturing the split gate non-volatile semiconductor memory device of JP-A-2004-214411 requires several additional manufacturing steps compared with that of JP-A-2004-200181 to result in a problem that the manufacturing cost is increased.
As shown in FIG. 10, the upper portion of the control gate 36 and surface layer of the drain diffusion region 33 are silicided for lowering the resistance. In this case, a side wall insulative film is formed on the side wall of the control gate 36 such that silicides are not short circuited to each other (silicide short circuit). That is, unless the side wall insulative wall is formed to a sufficient height, silicide short circuit may possibly occur. As described above, since the side wall insulative film is formed as the side wall of the control gate 36 by etching back, the height of the side wall insulative film depends on the height of the control gate 36. Further, since the control gate 36 is formed as the side wall of the second NSG spacer 40 by etching back, the height of the control gate 36 depends on the height of the second NSG spacer 40.
However, as shown in FIG. 11C, the first NSG spacer 39 is removed by wet etching using the 5% hydrofluoric acid.
The present inventor has recognized that since the upper portion of the second NSG spacer 40 is also exposed in this case, the second NSG spacer 40 is also etched simultaneously. Particularly, in JP-A-2004-200181, the first NSG spacer 39 is formed of a dense film and the second NSG spacer 40 is formed of the coarse film. That is, the etching rate for the second NSG spacer 40 is higher than the first NSG spacer 39. Therefore, since etching to the upper portion of the second NSG spacer 40 proceeds during removal of the first NSG spacer 39 and, as a result, the side wall insulating film is formed, this results in a problem that the necessary height for the second NSG spacer 40 cannot be ensured.